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ATMEGA128L-8AL 参数 Datasheet PDF下载

ATMEGA128L-8AL图片预览
型号: ATMEGA128L-8AL
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microcontroller, 8-Bit, FLASH, 8MHz, CMOS, PQFP64, 14 X 14 MM, 1 MM HEIGHT, 0.80 MM PITCH, PLASTIC, MS-026AEB, TQFP-64]
分类和应用: 时钟微控制器外围集成电路
文件页数/大小: 391 页 / 6192 K
品牌: ATMEL [ ATMEL ]
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ATmega128(L)  
Program flow is provided by conditional and unconditional jump and call instructions, able to  
directly address the whole address space. Most AVR instructions have a single 16-bit word for-  
mat. Every program memory address contains a 16- or 32-bit instruction.  
Program Flash memory space is divided in two sections, the Boot Program section and the  
Application Program section. Both sections have dedicated Lock bits for write and read/write  
protection. The SPM instruction that writes into the Application Flash Memory section must  
reside in the Boot Program section.  
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the  
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the stack  
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must  
initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack  
Pointer – SP – is read/write accessible in the I/O space. The data SRAM can easily be accessed  
through the five different addressing modes supported in the AVR architecture.  
The memory spaces in the AVR architecture are all linear and regular memory maps.  
A flexible interrupt module has its control registers in the I/O space with an additional global  
interrupt enable bit in the Status Register. All interrupts have a separate interrupt vector in the  
interrupt vector table. The interrupts have priority in accordance with their interrupt vector posi-  
tion. The lower the interrupt vector address, the higher the priority.  
The I/O memory space contains 64 addresses which can be accessed directly, or as the Data  
Space locations following those of the Register file, $20 - $5F. In addition, the ATmega128 has  
Extended I/O space from $60 - $FF in SRAM where only the ST/STS/STD and LD/LDS/LDD  
instructions can be used.  
ALU – Arithmetic  
Logic Unit  
The high-performance AVR ALU operates in direct connection with all the 32 general purpose  
working registers. Within a single clock cycle, arithmetic operations between general purpose  
registers or between a register and an immediate are executed. The ALU operations are divided  
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the  
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication  
and fractional format. See the “Instruction Set” section for a detailed description.  
Status Register  
The Status Register contains information about the result of the most recently executed arith-  
metic instruction. This information can be used for altering program flow in order to perform  
conditional operations. Note that the Status Register is updated after all ALU operations, as  
specified in the Instruction Set Reference. This will in many cases remove the need for using the  
dedicated compare instructions, resulting in faster and more compact code.  
The status register is not automatically stored when entering an interrupt routine and restored  
when returning from an interrupt. This must be handled by software.  
The AVR status Register – SREG – is defined as:  
Bit  
7
I
6
T
5
H
4
S
3
V
2
N
1
Z
0
C
SREG  
Read/Write  
Initial Value  
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
11  
2467P–AVR–08/07