ATmega640/1280/1281/2560/2561
Table 13-12. Overriding Signals for Alternate Functions PD7:PD4
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
PD7/T0
PD6/T1
PD5/XCK1
PD4/ICP1
0
0
0
0
0
0
0
0
0
0
XCK1 OUTPUT ENABLE
0
0
0
1
0
0
0
XCK1 OUTPUT ENABLE
0
0
0
XCK1 OUTPUT
0
0
0
0
0
0
T0 INPUT
–
0
T1 INPUT
–
0
0
XCK1 INPUT
ICP1 INPUT
AIO
–
–
Table 13-13. Overriding Signals for Alternate Functions in PD3:PD0(1)
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
PD3/INT3/TXD1
PD2/INT2/RXD1
PD1/INT1/SDA
TWEN
PD0/INT0/SCL
TWEN
TXEN1
RXEN1
0
PORTD2 • PUD
PORTD1 • PUD
TWEN
PORTD0 • PUD
TWEN
TXEN1
RXEN1
1
TXEN1
TXD1
0
SDA_OUT
TWEN
SCL_OUT
TWEN
0
0
0
0
INT3 ENABLE
1
INT2 ENABLE
INT1 ENABLE
1
INT0 ENABLE
1
1
INT3 INPUT
–
INT2 INPUT/RXD1
INT1 INPUT
SDA INPUT
INT0 INPUT
SCL INPUT
AIO
–
Note:
1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0
and PD1. This is not shown in this table. In addition, spike filters are connected between the
AIO outputs shown in the port figure and the digital logic of the TWI module.
85
2549L–AVR–08/07
ATMEL [ ATMEL ]
