ATmega640/1280/1281/2560/2561
Table 13-7 and Table 13-8 relate the alternate functions of Port B to the overriding signals
shown in Figure 13-5 on page 76. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
PCINT0, Pin Change Interrupt source 0: The PB0 pin can serve as an external interrupt source.
Table 13-7. Overriding Signals for Alternate Functions in PB7:PB4
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
PB7/OC0A/OC1C
PB6/OC1B
PB5/OC1A
PB4/OC2A
0
0
0
0
0
0
0
0
0
0
0
0
0
OC0/OC1C ENABLE
OC0/OC1C
PCINT7 • PCIE0
1
0
0
0
OC1B ENABLE
OC1A ENABLE
OC2A ENABLE
OC1B
OC1A
OC2A
PCINT6 • PCIE0
PCINT5 • PCIE0
PCINT4 • PCIE0
1
1
1
PCINT7 INPUT
–
PCINT6 INPUT
PCINT5 INPUT
PCINT4 INPUT
AIO
–
–
–
Table 13-8. Overriding Signals for Alternate Functions in PB3:PB0
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
PB3/MISO
SPE • MSTR
PORTB3 • PUD
SPE • MSTR
0
PB2/MOSI
SPE • MSTR
PORTB2 • PUD
SPE • MSTR
0
PB1/SCK
SPE • MSTR
PORTB1 • PUD
SPE • MSTR
0
PB0/SS
SPE • MSTR
PORTB0 • PUD
SPE • MSTR
0
SPE • MSTR
SPI SLAVE OUTPUT
PCINT3 • PCIE0
1
SPE • MSTR
SPI MSTR OUTPUT
PCINT2 • PCIE0
1
SPE • MSTR
SCK OUTPUT
PCINT1 • PCIE0
1
0
0
PCINT0 • PCIE0
1
SPI MSTR INPUT
PCINT3 INPUT
SPI SLAVE INPUT
PCINT2 INPUT
SCK INPUT
SPI SS
DI
PCINT1 INPUT
PCINT0 INPUT
AIO
–
–
–
–
81
2549L–AVR–08/07
ATMEL [ ATMEL ]
