Table 18-1 contains equations for calculating the baud rate (in bits per second) and for calculat-
ing the UBRR value for each mode of operation using an internally generated clock source.
Table 18-1. Equations for Calculating Baud Rate Register Setting
Equation for Calculating Baud
Rate(1)
Equation for Calculating UBRR
Value
Operating Mode
f
CLKio
Asynchronous Normal mode
(U2X = 0)
f
CLKio
BAUD = -----------------------------------------
UBRRn = ----------------------- – 1
16(UBRRn + 1)
16BAUD
f
CLKio
f
CLKio
Asynchronous Double Speed
mode (U2X = 1)
BAUD = --------------------------------------
UBRRn = -------------------- – 1
8(UBRRn + 1)
8BAUD
f
CLKio
f
CLKio
Synchronous Master mode
BAUD = --------------------------------------
UBRRn = -------------------- – 1
2(UBRRn + 1)
2BAUD
Note:
1. The baud rate is defined to be the transfer rate in bit per second (bps)
BAUD Baud rate (in bits per second, bps).
fclkio System I/O Clock frequency.
UBRR Contents of the UBRRH and UBRRL Registers, (0-4095).
Some examples of UBRR values for some system clock frequencies are found in Table 18-9
(see page 207).
18.3.2
Double Speed Operation (U2X)
The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only has effect
for the asynchronous operation. Set this bit to zero when using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling
the transfer rate for asynchronous communication. Note however that the Receiver will in this
case only use half the number of samples (reduced from 16 to 8) for data sampling and clock
recovery, and therefore a more accurate baud rate setting and system clock are required when
this mode is used. For the Transmitter, there are no downsides.
18.3.3
External Clock
External clocking is used by the synchronous slave modes of operation. The description in this
section refers to Figure 18-2 for details.
External clock input from the XCK pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector before it can be used by the Transmitter and Receiver. This process intro-
duces a two CPU clock period delay and therefore the maximum external XCK clock frequency
is limited by the following equation:
f
CLKio
---------------
f
<
XCKn
4
186
AT90PWM2/3/2B/3B
4317J–AVR–08/10
ATMEL [ ATMEL ]
