16.26 PSC2 Specific Register
16.26.1 PSC 2 Output Matrix – POM2
Bit
7
6
5
4
3
2
1
0
POMV2B3
POMV2B2
POMV2B1
POMV2B0
POMV2A3
POMV2A2
POMV2A1
POMV2A0
POM2
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
• Bit 7 – POMV2B3: Output Matrix Output B Ramp 3
This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 3
• Bit 6 – POMV2B2: Output Matrix Output B Ramp 2
This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 2
• Bit 5 – POMV2B1: Output Matrix Output B Ramp 1
This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 1
• Bit 4 – POMV2B0: Output Matrix Output B Ramp 0
This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 0
• Bit 3 – POMV2A3: Output Matrix Output A Ramp 3
This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 3
• Bit 2 – POMV2A2: Output Matrix Output A Ramp 2
This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 2
• Bit 1 – POMV2A1: Output Matrix Output A Ramp 1
This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 1
• Bit 0 – POMV2A0: Output Matrix Output A Ramp 0
This bit gives the state of the PSCOUT20 (and/or PSCOUT22) during ramp 0
16.26.2 PSC0 Interrupt Mask Register – PIM0
Bit
7
6
-
5
PSEIE0
R/W
0
4
PEVE0B
R/W
0
3
PEVE0A
R/W
0
2
-
1
-
0
PEOPE0
R/W
0
-
PIM0
Read/Write
Initial Value
R
0
R
0
R
0
R
0
16.26.3 PSC1 Interrupt Mask Register – PIM1
Bit
7
-
6
-
5
PSEIE1
R/W
0
4
PEVE1B
R/W
0
3
PEVE1A
R/W
0
2
-
1
-
0
PEOPE1
R/W
0
PIM1
Read/Write
Initial Value
R
0
R
0
R
0
R
0
170
AT90PWM2/3/2B/3B
4317J–AVR–08/10
ATMEL [ ATMEL ]
