16.18.1 Available Input Mode according to Running Mode
Some Input Modes are not consistent with some Running Modes. So the table below gives the
input modes which are valid according to running modes..
Table 16-7. Available Input Modes according to Running Modes
Input Mode
Number :
1 Ramp Mode
Valid
2 Ramp Mode
Valid
4 Ramp Mode
Valid
Centered Mode
Do not use
Do not use
Do not use
Valid
1
2
Do not use
Do not use
Valid
Valid
Valid
3
Valid
Valid
4
Valid
Valid
5
Do not use
Do not use
Valid
Valid
Valid
Do not use
Do not use
Valid
6
Valid
Valid
7
Valid
Valid
8
Valid
Valid
Valid
Do not use
Do not use
9
Valid
Valid
Valid
10
11
12
13
14
15
Do not use
Valid
Valid
Valid
Do not use
Do not use
16.18.2 Event Capture
The PSC can capture the value of time (PSC counter) when a retrigger event or fault event
occurs on PSC inputs. This value can be read by sofware in PICRnH/L register.
16.18.3 Using the Input Capture Unit
The main challenge when using the Input Capture unit is to assign enough processor capacity
for handling the incoming events. The time between two events is critical. If the processor has
not read the captured value in the PICRn Register before the next event occurs, the PICRn will
be overwritten with a new value. In this case the result of the capture will be incorrect.
When using the Input Capture interrupt, the PICRn Register should be read as early in the inter-
rupt handler routine as possible. Even though the Input Capture interrupt has relatively high
priority, the maximum interrupt response time is dependent on the maximum number of clock
cycles it takes to handle any of the other interrupt requests.
156
AT90PWM2/3/2B/3B
4317J–AVR–08/10
ATMEL [ ATMEL ]
