AT90PWM2/3/2B/3B
Figure 16-31. PSC behaviour versus PSCn Input A in Mode 8
DT0 OT0 DT0 OT0 DT0 OT0
DT1 OT1
DT1 OT1
DT1 OT1
PSCOUTn0
PSCOUTn1
PSCn Input A
The output frequency is modulated by the occurence of significative edge of retriggering input.
Figure 16-32. PSC behaviour versus PSCn Input B in Mode 8
DT0 OT0
DT0 OT0
DT0 OT0
DT1 OT1
DT1 OT1
DT1 OT1
PSCOUTn0
PSCOUTn1
PSCn Input B
or
PSCn Input B
The output frequency is modulated by the occurrence of significative edge of retriggering input.
The retrigger event is taken into account only if it occurs during the corresponding On-Time.
Note: In one ramp mode, the retrigger event on input A resets the whole ramp. So the PSC
doesn’t jump to the opposite dead-time.
16.17 PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC
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4317J–AVR–08/10
ATMEL [ ATMEL ]
