Figure 16-33. PSC behaviour versus PSCn Input A in Mode 9
DT0 OT0 DT0 OT0 DT0 OT0
DT1 OT1
DT1 OT1
DT1 OT1
PSCOUTn0
PSCOUTn1
PSCn Input A
The output frequency is not modified by the occurence of significative edge of retriggering input.
Only the output is disactivated when significative edge on retriggering input occurs.
Note: In this mode the output of the PSC becomes active during the next ramp even if the Retrig-
ger/Fault input is actve. Only the significative edge of Retrigger/Fault input is taken into account.
Figure 16-34. PSC behaviour versus PSCn Input B in Mode 9
DT0 OT0
DT0 OT0
DT0 OT0
DT1 OT1
DT1 OT1
DT1 OT1
PSCOUTn0
PSCOUTn1
PSCn Input B
The retrigger event is taken into account only if it occurs during the corresponding On-Time.
16.18 PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Disactivate Output
154
AT90PWM2/3/2B/3B
4317J–AVR–08/10
ATMEL [ ATMEL ]
