AT90PWM2/3/2B/3B
Figure 16-26. PSC behaviour versus PSCn Input A or Input B in Mode 4
DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0
DT1 OT1
PSCOUTn0
PSCOUTn1
PSCn Input A
or
PSCn Input B
Figure 16-27. PSC behaviour versus PSCn Input A or Input B in Fault Mode 4
DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1 DT0 OT0 DT1 OT1
PSCOUTn0
PSCOUTn1
PSCn Input A
or
PSCn Input B
PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on On-
Time1/Dead-Time1.
16.13 PSC Input Mode 5: Stop signal and Insert Dead-Time
Figure 16-28. PSC behaviour versus PSCn Input A in Fault Mode 5
DT0 OT0
DT0 OT0
DT0 OT0
DT1
OT1
DT1 OT1
DT1 OT1
PSCOUTn0
PSCOUTn1
PSCn Input A
or
PSCn Input B
Used in Fault mode 5, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0
or on On-Time1/Dead-Time1.
151
4317J–AVR–08/10
ATMEL [ ATMEL ]
