AT90PWM2/3/2B/3B
Type
Width
Description
Name
Register
4 bits
OCRnRB[1
5:12]
Frequency Resolution Enhancement value
(Flank Width Modulation)
CLK I/O
CLK PLL
SYnIn
Clock Input from I/O clock
Signal
Signal
Signal
Signal
Clock Input from PLL
Synchronization In (from adjacent PSC)(1)
StopIn
Stop Input (for synchronized mode)
Note:
1. See Figure 16-38 on page 158
Table 16-2. Block Inputs
Type
Width
Description
Name
PSCINn
from A C
Input 0 used for Retrigger or Fault functions
Input 1 used for Retrigger or Fault functions
Signal
Signal
16.4.2
Output Description
Table 16-3. Block Outputs
Type
Width
Description
Name
PSCOUTn0
PSCOUTn1
PSC n Output 0 (from part A of PSC)
PSC n Output 1 (from part B of PSC)
Signal
Signal
PSCOUTn2
(PSC2 only)
PSC n Output 2 (from part A or part B of PSC)
PSC n Output 3 (from part A or part B of PSC)
Signal
Signal
PSCOUTn3(
PSC2 only)
Table 16-4. Internal Outputs
Type
Width
Description
Name
SYnOut
Synchronization Output(1)
Signal
PICRn
[11:0]
PSC n Input Capture Register
Register
12 bits
Counter value at retriggering event
PSC Interrupt Request : three souces, overflow, fault, and input
capture
IRQPSCn
Signal
Signal
PSCnASY
StopOut
ADC Synchronization (+ Amplifier Syncho. )(2)
Stop Output (for synchronized mode)
Note:
1. See Figure 16-38 on page 158
2. See “Analog Synchronization” on page 157.
133
4317J–AVR–08/10
ATMEL [ ATMEL ]
