16.4 Signal Description
Figure 16-3. PSC External Block View
CLK
PLL
CLK
I/O
SYnIn
StopOut
12
12
12
12
4
OCRnRB[11:0]
OCRnSB[11:0]
OCRnRA[11:0]
OCRnSA[11:0]
OCRnRB[15:12]
PSCOUTn0
PSCOUTn1
PSCOUTn2
PSCOUTn3
(1)
(1)
(Flank Width
Modulation)
12
PICRn[11:0]
IRQ PSCn
PSCINn
Analog
Comparator
n Output
StopIn SYnOut PSCnASY
Note:
1. available only for PSC2
2. n = 0, 1 or 2
16.4.1
Input Description
Table 16-1. Internal Inputs
Type
Width
Description
Name
Register
OCRnRB[1
1:0]
Compare Value which Reset Signal on Part B (PSCOUTn1)
Compare Value which Set Signal on Part B (PSCOUTn1)
Compare Value which Reset Signal on Part A (PSCOUTn0)
Compare Value which Set Signal on Part A (PSCOUTn0)
12 bits
Register
12 bits
OCRnSB[1
1:0]
Register
12 bits
OCRnRA[1
1:0]
Register
12 bits
OCRnSA[1
1:0]
132
AT90PWM2/3/2B/3B
4317J–AVR–08/10
ATMEL [ ATMEL ]
