Table 4. Detailed Bit-level Addressing Sequence
Address Byte
Address Byte
Address Byte
Additional
Don’tCare
Bytes
Opcode
50H
52H
53H
54H
57H
58H
60H
68H
81H
82H
83H
84H
88H
D2H
D4H
D7H
Opcode
Required
0 1 0 1 0 0 0 0
0 1 0 1 0 0 1 0
0 1 0 1 0 0 1 1
0 1 0 1 0 1 0 0
0 1 0 1 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 0 0 0 0
0 1 1 0 1 0 0 0
1 0 0 0 0 0 0 1
1 0 0 0 0 0 1 0
1 0 0 0 0 0 1 1
1 0 0 0 0 1 0 0
1 0 0 0 1 0 0 0
1 1 0 1 0 0 1 0
1 1 0 1 0 1 0 0
1 1 0 1 0 1 1 1
1 1 1 0 1 0 0 0
r
r
r
r
r
r
r
r
r
r
r
r
P
P
P
x
P
P
P
x
P
P
P
x
P
P
P
x
P
P
P
x
P
P
P
x
x
x
x
x
B
x
x
B
x
x
B
x
x
B
x
x
B
x
x
B
x
x
B
x
x
B
x
x
B
x
N/A
4 Bytes
N/A
P
P
P
r
r
r
r
r
r
P
P
P
x
x
x
x
x
x
x
x
x
B
B
B
B
B
B
B
B
B
1 Byte
N/A
N/A
N/A
N/A
r
r
r
r
r
r
r
r
r
r
r
r
P
P
P
P
P
P
x
P
P
P
P
P
P
x
P
P
P
P
P
P
x
P
P
P
P
P
P
x
P
P
P
P
P
P
x
P
P
P
P
P
P
x
P
P
P
P
P
P
x
P
P
P
P
P
P
x
P
P
P
P
P
P
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
N/A
N/A
r
r
r
r
r
r
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
4 Bytes
N/A
r
r
r
r
r
r
r
r
r
r
r
r
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
N/A
r
r
r
r
r
r
N/A
x
r
x
r
x
r
x
r
x
r
x
r
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
B
x
N/A
P
P
x
P
P
x
P
P
x
P
P
x
P
P
x
P
P
x
P
P
x
P
P
x
P
P
x
N/A
r
r
r
r
r
r
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
4 Bytes
1 Byte
N/A
x
x
x
x
x
x
N/A
N/A
N/A
E8H
r
r
r
r
r
r
P
P
P
P
P
P
P
P
P
B
B
B
B
B
B
B
B
B
4 Bytes
Note:
r = Reserved Bit
P = Page Address Bit
B = Byte/Buffer Address Bit
x = Don’t Care
AT45DB011B
12
ATMEL [ ATMEL ]
