AC Timing Characteristics – 3.3V Operation AT40KLV
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: VCC = 3.0V, temperature = 70°C
Minimum times based on best case: VCC = 3.6V, temperature = 0°C
Cell Function
Async RAM
Write
Parameter
Path
-3
Units
Notes
tWECYC (Minimum)
cycle time
12.0
5.0
5.0
5.3
0.0
5.0
0.0
8.7
6.3
2.9
3.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write
tWEL (Minimum)
we
Pulse width low
Pulse width high
Write
t
WEH (Minimum)
AWS (Minimum)
we
Write
t
wr addr setup -> we
wr addr hold -> we
din setup -> we
din hold -> we
din -> dout
rd addr -> dout
oe -> dout
Write
tAWH (Minimum)
Write
t
DS (Minimum)
DH (Minimum)
Write
t
Write/Read
Read
tDD (Maximum)
rd addr = wr addr
tAD (Maximum)
tOZX (Maximum)
tOXZ (Maximum)
Read
Read
oe -> dout
Sync RAM
Write
t
CYC (Minimum)
cycle time
12.0
5.0
5.0
3.2
0.0
5.0
0.0
3.9
0.0
5.8
6.3
2.9
3.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write
tCLKL (Minimum)
clk
Pulse width low
Pulse width high
Write
tCLKH (Minimum)
tWCS(Minimum)
tWCH (Minimum)
tACS (Minimum)
tACH (Minimum)
tDCS (Minimum)
clk
Write
we setup -> clk
we hold -> clk
wr addr setup -> clk
wr addr hold -> clk
wr data setup -> clk
wr data hold -> clk
clk -> dout
Write
Write
Write
Write
Write
tDCH (Minimum)
Write/Read
Read
tCD (Maximum)
tAD (Maximum)
tOZX (Maximum)
tOXZ (Maximum)
rd addr = wr addr
rd addr -> dout
oe -> dout
Read
Read
oe -> dout
Notes: 1. CMOS buffer delays are measured from a VIH of 1/2 VCC at the pad to the internal VIH at A. The input buffer load is constant.
2. Buffer delay is to a pad voltage of 1.5V with one output switching.
3. Parameter based on characterization and simulation; not tested in production.
4. Exact power calculation is available in Atmel FPGA Designer software.
36
AT40K/AT40KLV Series FPGA
0896C–FPGA–04/02
ATMEL [ ATMEL ]
