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AT40K05LV-3DQI 参数 Datasheet PDF下载

AT40K05LV-3DQI图片预览
型号: AT40K05LV-3DQI
PDF下载: 下载PDF文件 查看货源
内容描述: 5K - 50K盖茨FPGA协处理器与FreeRAM [5K - 50K Gates Coprocessor FPGA with FreeRAM]
分类和应用: 现场可编程门阵列可编程逻辑异步传输模式ATM
文件页数/大小: 67 页 / 1491 K
品牌: ATMEL [ ATMEL ]
 浏览型号AT40K05LV-3DQI的Datasheet PDF文件第30页浏览型号AT40K05LV-3DQI的Datasheet PDF文件第31页浏览型号AT40K05LV-3DQI的Datasheet PDF文件第32页浏览型号AT40K05LV-3DQI的Datasheet PDF文件第33页浏览型号AT40K05LV-3DQI的Datasheet PDF文件第35页浏览型号AT40K05LV-3DQI的Datasheet PDF文件第36页浏览型号AT40K05LV-3DQI的Datasheet PDF文件第37页浏览型号AT40K05LV-3DQI的Datasheet PDF文件第38页  
AC Timing Characteristics 3.3V Operation AT40KLV  
Delays are based on fixed loads and are described in the notes.  
Maximum times based on worst case: VCC = 3.0V, temperature = 70°C  
Minimum times based on best case: VCC = 3.6V, temperature = 0°C  
Maximum delays are the average of tPDLH and tPDHL  
All input IO characteristics measured from a VIH of 50% of VDD at the pad (CMOS threshold) to the internal VIH of 50% of  
DD. All output IO characteristics are measured as the average of tPDLH and tPDHL to the pad VIH of 50% of VDD.  
.
V
Cell Function  
Parameter  
Path  
-3  
Units  
Notes  
Repeaters  
Repeater  
Repeater  
Repeater  
Repeater  
Repeater  
Repeater  
t
PD (Maximum)  
L -> E  
E -> E  
L -> L  
E -> L  
E -> IO  
L -> IO  
2.2  
2.2  
2.2  
2.2  
1.4  
1.4  
ns  
ns  
ns  
ns  
ns  
ns  
1 unit load  
1 unit load  
1 unit load  
1 unit load  
1 unit load  
1 unit load  
tPD (Maximum)  
t
PD (Maximum)  
PD (Maximum)  
t
tPD (Maximum)  
PD (Maximum)  
t
All input IO characteristics measured from a VIH of 50% of VDD at the pad (CMOS threshold) to the internal VIH of 50% of  
DD. All output IO characteristics are measured as the average of tPDLH and tPDHL to the pad VIH of 50% of VDD.  
V
Cell Function  
Parameter  
Path  
-3  
Units  
Notes  
IO  
Input  
t
t
t
PD (Maximum)  
PD (Maximum)  
PD (Maximum)  
pad -> x/y  
pad -> x/y  
pad -> x/y  
pad -> x/y  
x/y/E/L -> pad  
x/y/E/L -> pad  
x/y/E/L -> pad  
oe -> pad  
1.9  
5.8  
11.5  
17.4  
9.1  
7.6  
6.2  
9.5  
2.1  
7.4  
2.7  
5.9  
2.4  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
No extra delay  
1 extra delay  
2 extra delays  
3 extra delays  
50 pf load  
Input  
Input  
Input  
tPD (Maximum)  
Output, Slow  
Output, Medium  
Output, Fast  
Output, Slow  
Output, Slow  
Output, Medium  
Output, Medium  
Output, Fast  
Output, Fast  
tPD (Maximum)  
tPD (Maximum)  
tPD (Maximum)  
tPZX (Maximum)  
tPXZ (Maximum)  
50 pf load  
50 pf load  
50 pf load  
oe -> pad  
50 pf load  
tPZX (Maximum)  
oe -> pad  
50 pf load  
tPXZ (Maximum)  
tPZX (Maximum)  
tPXZ (Maximum)  
oe -> pad  
50 pf load  
oe -> pad  
50 pf load  
oe -> pad  
50 pf load  
34  
AT40K/AT40KLV Series FPGA  
0896CFPGA04/02  
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