AT40K/AT40KLV Series FPGA
AC Timing Characteristics – 3.3V Operation AT40KLV
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: VCC = 3.00V, temperature = 70°C
Minimum times based on best case: VCC = 3.60V, temperature = 0°C
Maximum delays are the average of tPDLH and tPDHL
.
Cell Function
Core
Parameter
Path
-3
Units
Notes
2-input Gate
3-input Gate
3-input Gate
4-input Gate
Fast Carry
Fast Carry
Fast Carry
Fast Carry
Fast Carry
Fast Carry
Fast Carry
Fast Carry
DFF
t
PD (Maximum)
x/y -> x/y
x/y/z -> x/y
x/y/w -> x/y
x/y/w/z -> x/y
y -> y
2.9
2.8
3.4
3.4
2.3
2.9
3.0
2.3
3.4
3.4
3.4
2.4
2.8
3.2
3.0
2.7
2.4
2.8
2.4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
1 unit load
tPD (Maximum)
t
PD (Maximum)
PD (Maximum)
t
tPD (Maximum)
t
PD (Maximum)
PD (Maximum)
x -> y
t
y -> x
tPD (Maximum)
x -> x
tPD (Maximum)
tPD (Maximum)
tPD (Maximum)
tPD (Maximum)
tPD (Maximum)
w -> y
w -> x
z -> y
z -> x
q -> x/y
R -> x/y
S -> x/y
q -> w
DFF
tPD (Maximum)
DFF
tPD (Maximum)
tPD (Maximum)
tPD (Maximum)
tPZX (Maximum)
tPXZ (Maximum)
DFF
Incremental -> L
Local Output Enable
Local Output Enable
x/y -> L
oe -> L
oe -> L
1 unit load
1 unit load
33
0896C–FPGA–04/02
ATMEL [ ATMEL ]
