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Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.
Figure 13-2. Prescaler for synchronous Timer/Counters
clkI/O
Clear
PSR10
Tn
Synchronization
Tn
Synchronization
CSn0
CSn1
CSn2
CSn0
CSn1
CSn2
TIMER/COUNTERn CLOCK SOURCE
clkTn
TIMER/COUNTERn CLOCK SOURCE
clkTn
13.0.4
General Timer/Counter Control Register – GTCCR
Bit
7
6
–
5
–
4
–
3
–
2
–
1
-
0
TSM
PSRSY
NC
GTCCR
Read/Write
Initial Value
R/W
0
R
0
R
0
R
0
R
0
R
0
R/W
0
R/W
0
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the correspond-
ing prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are
halted and can be configured to the same value without the risk of one of them advancing during
configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared
by hardware, and the Timer/Counters start counting simultaneously.
• Bit 0 – PSRSYNC: Prescaler Reset for Synchronous Timer/Counters
When this bit is one, Timer/Counter0 and Timer/Counter1, Timer/Counter3, Timer/Counter4 and
Timer/Counter5 prescaler will be Reset. This bit is normally cleared immediately by hardware,
except if the TSM bit is set. Note that Timer/Counter0 and Timer/Counter1 share the same pres-
caler and a reset of this prescaler will affect all timers.
89
7707D–AVR–07/08
ATMEL [ ATMEL ]
