AT90USB82/162
When a logic change on any PCINT12..8/7..0 pin triggers an interrupt request, PCIF1/0
becomes set (one). If the I-bit in SREG and the PCIE1/0 bit in EIMSK are set (one), the MCU will
jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is exe-
cuted. Alternatively, the flag can be cleared by writing a logical one to it.
12.0.7
Pin Change Mask Register 0 – PCMSK0
Bit
7
6
5
4
3
2
1
0
PCINT7
PCINT6
PCINT5
R/W
0
PCINT4
R/W
0
PCINT3
R/W
0
PCINT2
R/W
0
PCINT1
R/W
0
PCINT0
R/W
0
PCMSK0
Read/Write
Initial Value
R/W
0
R/W
0
• Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0
Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT7..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin
is disabled.
12.0.8
Pin Change Mask Register 1– PCMSK1
Bit
7
6
5
4
3
2
1
0
-
-
-
PCINT12
PCINT11
PCINT10
PCINT9
R/W
0
PCINT8
R/W
0
PCMSK1
Read/Write
Initial Value
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
• Bit 4..0 – PCINT12..8: Pin Change Enable Mask 12..8
Each PCINT12..8 bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT12..8 is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT12..8 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
87
7707D–AVR–07/08
ATMEL [ ATMEL ]
