AT90USB64/128
• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 6-0 - EPRST6:0 - Endpoint FIFO Reset Bits
Set to reset the selected endpoint FIFO prior to any other operation, upon hardware reset or
when an USB bus reset has been received. See Section 22.4, page 270 for more information
Then, cleared by software to complete the reset operation and start using the endpoint.
Bit
7
-
6
-
5
4
3
RSTDT
W
2
-
1
-
0
EPEN
R/W
0
STALLRQ STALLRQC
UECONX
Read/Write
Initial Value
R
0
R
0
W
0
W
0
R
0
R
0
0
• 7-6 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 5 - STALLRQ - STALL Request Handshake Bit
Set to request a STALL answer to the host for the next handshake.
Cleared by hardware when a new SETUP is received. Clearing by software has no effect.
See Section 22.12, page 273 for more details.
• 4 - STALLRQC - STALL Request Clear Handshake Bit
Set to disable the STALL handshake mechanism.
Cleared by hardware immediately after the set. Clearing by software has no effect.
See Section 22.12, page 273 for more details.
3
• RSTDT - Reset Data Toggle Bit
Set to automatically clear the data toggle sequence:
For OUT endpoint: the next received packet will have the data toggle 0.
For IN endpoint: the next packet to be sent will have the data toggle 0.
Cleared by hardware instantaneously. The firmware does not have to wait that the bit is cleared.
Clearing by software has no effect.
• 2 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 1 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 0 - EPEN - Endpoint Enable Bit
Set to enable the endpoint according to the device configuration. Endpoint 0 shall always be
enabled after a hardware or USB reset and participate in the device configuration.
Clear this bit to disable the endpoint. See Section 22.7, page 270 for more details.
285
7593A–AVR–02/06
ATMEL [ ATMEL ]
