ADDEN is cleared by hardware:
• after a power-up reset,
• when an USB reset is received,
• or when the macro is disabled (USBE cleared)
When this bit is cleared, the default device address 00h is used.
22.9 Suspend, Wake-up and Resume
After a period of 3 ms during which the USB line was inactive, the controller switches to the full-
speed mode and triggers (if enabled) the SUSPI (suspend) interrupt. The firmware may then set
the FRZCLK bit.
The CPU can also, depending on software architecture, enter in the idle mode to lower again the
power consumption.
There are two ways to recover from the “Suspend” mode:
• First one is to clear the FRZCLK bit. This is possible if the CPU is not in the Idle mode.
• Second way, if the CPU is “idle”, is to enable the WAKEUPI interrupt (WAKEUPE set). Then,
as soon as an non-idle signal is seen by the controller, the WAKEUPI interrupt is triggered.
The firmware shall then clear the FRZCLK bit to restart the transfer.
There are no relationship between the SUSPI interrupt and the WAKEUPI interrupt: the WAKE-
UPI interrupt is triggered as soon as there are non-idle patterns on the data lines. Thus, the
WAKEUPI interrupt can occurs even if the controller is not in the “suspend” mode.
When the WAKEUPI interrupt is triggered, if the SUSPI interrupt bit was already set, it is cleared
by hardware.
When the SUSPI interrupt is triggered, if the WAKEUPI interrupt bit was already set, it is cleared
by hardware.
22.10 Detach
The reset value of the DETACH bit is 1.
It is possible to re-enumerate a device, simply by setting and clearing the DETACH bit.
• If the USB device controller is in full-speed mode, setting DETACH will disconnect the pull-up
on the D+ or D- pad (depending on full or low speed mode selected). Then, clearing DETACH
will connect the pull-up on the D+ or D- pad.
Figure 22-3. Detach a device in Full-speed:
UVREF
UVREF
D +
D -
D +
D -
Detach, then
Attach
EN=1
EN=1
272
AT90USB64/128
7593A–AVR–02/06
ATMEL [ ATMEL ]
