AT90USB64/128
22.13.2 Control Read
The next figure shows a control read transaction. The USB controller has to manage the simulta-
neous write requests from the CPU and the USB host:
SETUP
SETUP
HW
DATA
STATUS
USB line
RXSTPI
RXOUTI
TXINI
IN
IN
OUT
NAK
OUT
SW
HW
SW
SW
HW
SW
Wr Enable
HOST
Wr Enable
CPU
A NAK handshake is always generated at the first status stage command.
When the controller detect the status stage, all the data writen by the CPU are erased, and
clearing TXINI has no effects.
The firmware checks if the transmission is complete or if the reception is complete.
The OUT retry is always ack’ed. This reception:
- set the RXOUTI flag (received OUT data)
- set the TXINI flag (data sent, ready to accept new data)
software algorithm:
set transmit ready
wait (transmit complete OR Receive complete)
if receive complete, clear flag and return
if transmit complete, continue
Once the OUT status stage has been received, the USB controller waits for a SETUP request.
The SETUP request have priority over any other request and has to be ACK’ed. This means that
any other flag should be cleared and the fifo reset when a SETUP is received.
WARNING: the byte counter is reset when the OUT Zero Length Packet is received. The firm-
ware has to take care of this.
22.14 OUT endpoint management
OUT packets are sent by the host. All the data can be read by the CPU, which acknowledges or
not the bank when it is empty.
22.14.1 Overview
The Endpoint must be configured first.
Each time the current bank is full, the RXOUTI and the FIFOCON bits are set. This triggers an
interrupt if the RXOUTE bit is set. The firmware can acknowledge the USB interrupt by clearing
the RXOUTI bit. The Firmware read the data and clear the FIFOCON bit in order to free the cur-
rent bank. If the OUT Endpoint is composed of multiple banks, clearing the FIFOCON bit will
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7593A–AVR–02/06
ATMEL [ ATMEL ]
