switch to the next bank. The RXOUTI and FIFOCON bits are then updated by hardware in
accordance with the status of the new bank.
RXOUTI shall always be cleared before clearing FIFOCON.
The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can
read data from the bank, and cleared by hardware when the bank is empty.
Example with 1 OUT data bank
DATA
(to bank 0)
NAK
DATA
(to bank 0)
OUT
ACK
HW
OUT
ACK
HW
RXOUTI
SW
SW
read data from CPU
BANK 0
FIFOCON
SW
read data from CPU
BANK 0
Example with 2 OUT data banks
DATA
OUT
DATA
(to bank 1)
ACK
HW
OUT
ACK
(to bank 0)
HW
RXOUTI
SW
SW
read data from CPU
BANK 0
SW
FIFOCON
read data from CPU
BANK 1
22.14.2 Detailed description
22.14.2.1
The data are read by the CPU, following the next flow:
• When the bank is filled by the host, an endpoint interrupt (EPINTx) is triggered, if enabled
(RXOUTE set) and RXOUTI is set. The CPU can also poll RXOUTI or FIFOCON, depending
on the software architecture,
• The CPU acknowledges the interrupt by clearing RXOUTI,
• The CPU can read the number of byte (N) in the current bank (N=BYCT),
• The CPU can read the data from the current bank (“N” read of UEDATX),
• The CPU can free the bank by clearing FIFOCON when all the data is read, that is:
• after “N” read of UEDATX,
• as soon as RWAL is cleared by hardware.
If the endpoint uses 2 banks, the second one can be filled by the HOST while the current one is
being read by the CPU. Then, when the CPU clear FIFOCON, the next bank may be already
ready and RXOUTI is set immediately.
276
AT90USB64/128
7593A–AVR–02/06
ATMEL [ ATMEL ]
