21.6.2
Host mode
When the USB interface is configured in device mode, internal Pull Down resistors are activated
on both UDP UDM lines and the interface detects the type of device connected.
21.7 Memory access capability
The CPU has the possibility to directly access to the USB internal memory (DPRAM).
The memory access mode is performed using 2 sfr’s: UDPADDH and UDPADDL.
To enter in this mode:
• the USBE bit must be cleared.
• the DPACC bit and the base address DPADD10:0 must be set.
Even if the USBE bit is cleared, the DPACC bit and DPADD10:0 field can be used by the
firmware.
Then, a read or a write in UEDATX (device mode) or in UPDATX (host mode) is performed
according to DPADD10:0 and the base address DPADD10:0 field is automatically increased.
The endpoint FIFO pointers and the value of the UxNUM registers are discarded in this mode.
The aim of this functionality is to use the DPRAM as extra-memory.
When using this mode, there is no influence over the USB controller.
Unused
[DPADDH - DPADDL]
Endpoint 1 to N
Endpoint 0
USB DPRAM
21.8 Memory management
The controller does only support the following memory allocation management:
The reservation of a Pipe or an Endpoint can only be made in the growing order (Pipe/Endpoint
0 to the last Pipe/Endpoint). The firmware shall thus configure them in the same order.
The reservation of a Pipe or an Endpoint “ki” is done when its ALLOC bit is set. Then, the hard-
ware allocates the memory and insert it between the Pipe/Endpoints “ki-1” and “ki+1”. The “ki+1
”
Pipe/Endpoint memory “slides” up and its data is lost. Note that the “ki+2” and upper Pipe/End-
point memory does not slide.
Clearing a Pipe enable (PEN) or an Endpoint enable (EPEN) does not clear neither its ALLOC
bit, nor its configuration (EPSIZE/PSIZE, EPBK/PBK). To free its memory, the firmware should
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ATMEL [ ATMEL ]
