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• the HWUPI interrupt is triggered in the Host mode (HOST set).
• the IDTI interrupt is triggered
• the VBUSTI interrupt is triggered
21.5.3
Freeze clock
The firmware has the ability to reduce the power consumption by setting the FRZCLK bit, which
freeze the clock of USB controller. When FRZCLK is set, it is still possible to access to the fol-
lowing registers:
• USBCON, USBSTA, USBINT
• DPRAM direct access (DPADD10:0, UxDATX)
• UDCON (detach, ...)
• UDINT
• UDIEN
• UHCON
• UHINT
• UHIEN
Moreover, when FRZCLK is set, only the following interrupts may be triggered:
• WAKEUPI
• IDTI
• VBUSTI
• HWUPI
21.6 Speed Control
21.6.1
Device mode
When the USB interface is configured in device mode, the speed selection (Full Speed or Low
Speed) depends on the UDP/UDM pull-up. UDSS register allows to select an internal pull up on
UDM (Low Speed mode) or UDP(Full Speed mode) data lines. UDSS should be configure
before attaching the device.
Figure 21-14. Device mode Speed Selection
USB
Regulator
UCAP
DETACH
UDCON.0
LSM
UDCON.2
UDP
UDM
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