AT90S1200
Watchdog Timer
The Watchdog Timer is clocked from a separate On-chip Oscillator that runs at 1 MHz.
This is the typical value at VCC = 5V. See characterization data for typical values at other
VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval
can be adjusted, see Table 6 for a detailed description. The WDR (Watchdog Reset)
instruction resets the Watchdog Timer. Eight different clock cycle periods can be
selected to determine the maximum period between two WDR instructions to prevent
the Watchdog Timer from resetting the MCU. If the reset period expires without another
WDR instruction, the AT90S1200 resets and executes from the Reset Vector. For timing
details on the Watchdog Reset, refer to page 14.
Figure 20. Watchdog Timer
Watchdog Timer Control
Register – WDTCR
Bit
7
–
6
–
5
–
4
–
3
WDE
R/W
0
2
WDP2
R/W
0
1
WDP1
R/W
0
0
WDP0
R/W
0
$21
WDTCR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
• Bits 7..4 – Res: Reserved Bits
These bits are reserved bits in the AT90S1200 and will always read as zero.
• Bit 3 – WDE: Watchdog Enable
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared
(zero) the Watchdog Timer function is disabled.
• Bits 2..0 – WDP2..0: Watchdog Timer Prescaler 2, 1 and 0
The WDP2..0 determine the Watchdog Timer prescaling when the Watchdog Timer is
enabled. The different prescaling values and their corresponding timeout periods are
shown in Table 6.
23
0838H–AVR–03/02
ATMEL [ ATMEL ]
