Table 6. Watchdog Timer Prescale Select
Number of WDT
WDP0 Oscillator Cycles
Typical Time-out
at VCC = 3.0V
Typical Time-out
at VCC = 5.0V
WDP2
WDP1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
16K cycles
47 ms
94 ms
0.19 s
0.38 s
0.75 s
1.5 s
15 ms
30 ms
60 ms
0.12 s
0,24 s
0.49 s
0.97 s
1.9 s
32K cycles
64K cycles
128K cycles
256K cycles
512K cycles
1,024K cycles
2,048K cycles
3.0 s
6.0 s
Note:
The frequency of the Watchdog Oscillator is voltage dependent as shown in “Typical
Characteristics” on page 51.
The WDR (Watchdog Reset) instruction should always be executed before the Watchdog
Timer is enabled. This ensures that the reset period will be in accordance with the
Watchdog Timer prescale settings. If the Watchdog Timer is enabled without Reset, the
Watchdog Timer may not start to count from zero.
To avoid unintentional MCU resets, the Watchdog Timer should be disabled or reset
before changing the Watchdog Timer Prescale Select.
24
AT90S1200
0838H–AVR–03/02
ATMEL [ ATMEL ]
