• Bits 2, 1, 0 – CS02, CS01, CS00: Clock Select0, Bits 2, 1 and 0
The Clock Select0 bits 2, 1 and 0 define the prescaling source of Timer/Counter0.
Table 5. Clock 0 Prescale Select
CS02
CS01
CS00
Description
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Stop, the Timer/Counter0 is stopped.
CK
CK/8
CK/64
CK/256
CK/1024
External Pin T0, falling edge
External Pin T0, rising edge
The Stop condition provides a Timer Enable/Disable function. The CK down divided
modes are scaled directly from the CK Oscillator clock. If the external pin modes are
used for Timer/Counter0, transitions on PD4/(T0) will clock the counter even if the pin is
configured as an output. This feature can give the user SW control of the counting.
Timer/Counter0 – TCNT0
Bit
7
MSB
R/W
0
6
5
4
3
2
1
0
$32
LSB
R/W
0
TCNT0
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
The Timer/Counter0 is realized as an up-counter with read and write access. If the
Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues
counting in the timer clock cycle following the write operation.
22
AT90S1200
0838H–AVR–03/02
ATMEL [ ATMEL ]
