I/O Memory
The I/O space definition of the AT90S1200 is shown in the following table.
Table 1. The AT90S1200 I/O Space
Address Hex
$3F
Name
SREG
GIMSK
TIMSK
TIFR
Function
Status REGister
$3B
$39
General Interrupt MaSK register
Timer/Counter Interrupt MaSK register
Timer/Counter Interrupt Flag register
MCU general Control Register
Timer/Counter0 Control Register
Timer/Counter0 (8-bit)
$38
$35
MCUCR
TCCR0
TCNT0
WDTCR
EEAR
EEDR
EECR
PORTB
DDRB
PINB
$33
$32
$21
Watchdog Timer Control Register
EEPROM Address Register
EEPROM Data Register
$1E
$1D
$1C
$18
EEPROM Control Register
Data Register, Port B
$17
Data Direction Register, Port B
Input Pins, Port B
$16
$12
PORTD
DDRD
PIND
Data Register, Port D
$11
Data Direction Register, Port D
Input Pins, Port D
$10
$08
ACSR
Analog Comparator Control and Status Register
Note:
Reserved and unused locations are not shown in the table.
All AT90S1200 I/Os and peripherals are placed in the I/O space. The different I/O loca-
tions are accessed by the IN and OUT instructions transferring data between the 32
general purpose working registers and the I/O space. I/O registers within the address
range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instruc-
tions. Refer to the instruction set chapter for more details.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that the CBI
and SBI instructions will operate on all bits in the I/O register, writing a one back into any
flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers
$00 to $1F only.
The different I/O and peripherals control registers are explained in the following
sections.
10
AT90S1200
0838H–AVR–03/02
ATMEL [ ATMEL ]
