During interrupts and subroutine calls, the return address Program Counter (PC) is
stored on the stack. The stack is a 3-level-deep hardware stack dedicated for subrou-
tines and interrupts.
The I/O memory space contains 64 addresses for CPU peripheral functions such as
Control Registers, Timer/Counters, A/D Converters and other I/O functions. The mem-
ory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional
global interrupt enable bit in the status register. All the different interrupts have a sepa-
rate interrupt vector in the interrupt vector table at the beginning of the
program memory. The different interrupts have priority in accordance with their interrupt
vector position. The lower the interrupt vector address, the higher the priority.
General Purpose
Register File
Figure 5 shows the structure of the 32 general purpose registers in the CPU.
Figure 5. AVR CPU General Purpose Working Registers
7
0
R0
R1
R2
General
Purpose
Working
Registers
…
…
R28
R29
R30 (Z-Register)
R31
All the register operating instructions in the instruction set have direct and single cycle
access to all registers. The only exception is the five constant arithmetic and logic
instructions SBCI, SUBI, CPI, ANDI, ORI between a constant and a register and the LDI
instruction for load immediate constant data. These instructions apply to the second half
of the registers in the register file (R16..R31). The general SBC, SUB, CP, AND, OR
and all other operations between two registers or on a single register apply to the entire
register file.
Register 30 also serves as an 8-bit pointer for indirect address of the register file.
ALU – Arithmetic Logic
Unit
The high-performance AVR ALU operates in direct connection with all the 32 general
purpose working registers. Within a single clock cycle, ALU operations between regis-
ters in the register file are executed. The ALU operations are divided into three main
categories – arithmetic, logic and bit-functions.
In-System
Programmable Flash
Program Memory
The AT90S1200 contains 1K bytes On-chip In-System Programmable Flash memory for
program storage. Since all instructions are single 16-bit words, the Flash is organized as
512 x 16. The Flash memory has an endurance of at least 1000 write/erase cycles.
The AT90S1200 Program Counter is 9 bits wide, thus addressing the 512 words Flash
program memory.
See page 37 for a detailed description on Flash data downloading.
6
AT90S1200
0838H–AVR–03/02
ATMEL [ ATMEL ]
