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90S1200 参数 Datasheet PDF下载

90S1200图片预览
型号: 90S1200
PDF下载: 下载PDF文件 查看货源
内容描述: 8 -bit微控制器1K字节的系统内可编程闪存 [8-Bit Microcontroller with 1K bytes In-System Programmable Flash]
分类和应用: 闪存微控制器
文件页数/大小: 71 页 / 1365 K
品牌: ATMEL [ ATMEL ]
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AT90S1200  
Status Register SREG  
The AVR status register (SREG) at I/O space location $3F is defined as:  
Bit  
7
I
6
T
5
H
4
S
3
V
2
N
1
Z
0
C
$3F  
SREG  
Read/Write  
Initial Value  
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
Bit 7 I: Global Interrupt Enable  
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The  
individual interrupt enable control is then performed in separate control registers. If the  
global interrupt enable bit is cleared (zero), none of the interrupts are enabled indepen-  
dent of the individual interrupt enable settings. The I-bit is cleared by hardware after an  
interrupt has occurred, and is set by the RETI instruction to enable subsequent  
interrupts.  
Bit 6 T: Bit Copy Storage  
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source  
and destination for the operated bit. A bit from a register in the register file can be copied  
into T by the BST instruction, and a bit in T can be copied into a bit in a register in the  
register file by the BLD instruction.  
Bit 5 H: Half-carry Flag  
The half-carry flag H indicates a half carry in some arithmetic operations. See the  
Instruction Set description for detailed information.  
Bit 4 S: Sign Bit, S = NV  
The S-bit is always an exclusive or between the negative flag N and the twos comple-  
ment overflow flag V. See the Instruction Set description for detailed information.  
Bit 3 V: Twos Complement Overflow Flag  
The twos complement overflow flag V supports twos complement arithmetics. See the  
Instruction Set description for detailed information.  
Bit 2 N: Negative Flag  
The negative flag N indicates a negative result after the different arithmetic and logic  
operations. See the Instruction Set description for detailed information.  
Bit 1 Z: Zero Flag  
The zero flag Z indicates a zero result after the different arithmetic and logic operations.  
See the Instruction Set description for detailed information.  
Bit 0 C: Carry Flag  
The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction  
Set description for detailed information.  
Note that the status register is not automatically stored when entering an interrupt rou-  
tine and restored when returning from an interrupt routine. This must be handled by  
software.  
11  
0838HAVR03/02