been applied, the Power-on Reset period can be extended. Refer to Figure 15 for a tim-
ing example on this.
Figure 15. MCU Start-up, RESET Controlled Externally
VPOT
VCC
VRST
RESET
tTOUT
TIME-OUT
INTERNAL
RESET
External Reset
An External Reset is generated by a low level on the RESET pin. Reset pulses longer
than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not
guaranteed to generate a reset. When the applied signal reaches the Reset Threshold
Voltage (VRST) on its positive edge, the delay timer starts the MCU after the Time-out
period tTOUT has expired.
Figure 16. External Reset during Operation
VCC
RESET
TIME-OUT
INTERNAL
RESET
Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle dura-
tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period
tTOUT. Refer to page 23 for details on operation of the Watchdog.
14
AT90S1200
0838H–AVR–03/02
ATMEL [ ATMEL ]
