AT89C5115
Registers
Table 37. TCON Register
TCON (S:88h)
Timer/Counter Control Register
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Bit
Bit
Number
Mnemonic Description
Timer 1 Overflow Flag
Cleared by hardware when processor vectors to interrupt routine.
Set by hardware on Timer/Counter overflow, when Timer 1 register overflows.
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
Timer 1 Run Control bit
Clear to turn off Timer/Counter 1.
Set to turn on Timer/Counter 1.
Timer 0 Overflow Flag
Cleared by hardware when processor vectors to interrupt routine.
Set by hardware on Timer/Counter overflow, when Timer 0 register overflows.
Timer 0 Run Control bit
Clear to turn off Timer/Counter 0.
Set to turn on Timer/Counter 0.
Interrupt 1 Edge Flag
Cleared by hardware when interrupt is processed if edge-triggered (See IT1).
Set by hardware when external interrupt is detected on INT1# pin.
Interrupt 1 Type Control bit
Clear to select low level active (level triggered) for external interrupt 1 (INT1#).
Set to select falling edge active (edge triggered) for external interrupt 1.
IT1
Interrupt 0 Edge Flag
Cleared by hardware when interrupt is processed if edge-triggered (See IT0).
Set by hardware when external interrupt is detected on INT0# pin.
IE0
Interrupt 0 Type Control bit
Clear to select low level active (level triggered) for external interrupt 0 (INT0#).
Set to select falling edge active (edge triggered) for external interrupt 0.
IT0
Reset Value = 0000 0000b
59
4128F–8051–05/06
ATMEL [ ATMEL ]
