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89C5115-TISUM 参数 Datasheet PDF下载

89C5115-TISUM图片预览
型号: 89C5115-TISUM
PDF下载: 下载PDF文件 查看货源
内容描述: [Microcontroller, 8-Bit, FLASH, 40MHz, CMOS, PDSO28, SOIC-28]
分类和应用: 时钟ATM异步传输模式微控制器光电二极管外围集成电路
文件页数/大小: 113 页 / 730 K
品牌: ATMEL [ ATMEL ]
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AT89C5115  
Exiting Power-down Mode  
Note:  
If VDD was reduced during the Power-down mode, do not exit Power-down mode until  
V
DD is restored to the normal operating level.  
There are two ways to exit the Power-down mode:  
1. Generate an enabled external interrupt.  
The T89C5115 provides capability to exit from Power-down using INT0#,  
INT1#.  
Hardware clears PD bit in PCON register which starts the oscillator and  
restores the clocks to the CPU and peripherals. Using INTx# input,  
execution resumes when the input is released (See Figure 8). Execution  
resumes with the interrupt service routine. Upon completion of the interrupt  
service routine, program execution resumes with the instruction immediately  
following the instruction that activated Power-down mode.  
Notes: 1. The external interrupt used to exit Power-down mode must be configured as level  
sensitive (INT0# and INT1#) and must be assigned the highest priority. In addition,  
the duration of the interrupt must be long enough to allow the oscillator to stabilize.  
The execution will only resume when the interrupt is deasserted.  
2. Exit from power-down by external interrupt does not affect the SFRs nor the internal  
RAM content.  
Figure 8. Power-down Exit Waveform Using INT1:0#  
INT1:0#  
OSC  
Active phase  
Power-down phase  
Oscillator restart phase  
Active phase  
2. Generate a reset.  
A logic high on the RST pin clears PD bit in PCON register directly and  
asynchronously. This starts the oscillator and restores the clock to the CPU  
and peripherals. Program execution momentarily resumes with the  
instruction immediately following the instruction that activated Power-down  
mode and may continue for a number of clock cycles before the internal  
reset algorithm takes control. Reset initializes the T89C5115 and vectors the  
CPU to address 0000h.  
Notes: 1. During the time that execution resumes, the internal RAM cannot be accessed; how-  
ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at  
the Port pins, the instruction immediately following the instruction that activated the  
Power-down mode should not write to a Port pin or to the external RAM.  
2. Exit from power-down by reset redefines all the SFRs, but does not affect the internal  
RAM content.  
21  
4128F–8051–05/06  
 
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