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89C5115-TISUM 参数 Datasheet PDF下载

89C5115-TISUM图片预览
型号: 89C5115-TISUM
PDF下载: 下载PDF文件 查看货源
内容描述: [Microcontroller, 8-Bit, FLASH, 40MHz, CMOS, PDSO28, SOIC-28]
分类和应用: 时钟ATM异步传输模式微控制器光电二极管外围集成电路
文件页数/大小: 113 页 / 730 K
品牌: ATMEL [ ATMEL ]
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Power Management  
Reset Pin  
Two power reduction modes are implemented in the T89C5115: the Idle mode and the  
Power-down mode. These modes are detailed in the following sections. In addition to  
these power reduction modes, the clocks of the core and peripherals can be dynamically  
divided by 2 using the X2 Mode detailed in Section “Clock”.  
In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, a  
high level has to be applied on the RST pin. A bad level leads to a wrong initialisation of  
the internal registers like SFRs, PC, etc. and to unpredictable behavior of the microcon-  
troller. A warm reset can be applied either directly on the RST pin or indirectly by an  
internal reset source such as a watchdog, PCA, timer, etc.  
At Power-up (cold reset) Two conditions are required before enabling a CPU start-up:  
VDD must reach the specified VDD range,  
The level on xtal1 input must be outside the specification (VIH, VIL).  
If one of these two conditions are not met, the microcontroller does not start correctly  
and can execute an instruction fetch from anywhere in the program space. An active  
level applied on the RST pin must be maintained until both of the above conditions are  
met. A reset is active when the level VIH1 is reached and when the pulse width covers  
the period of time where VDD and the oscillator are not stabilized. Two parameters have  
to be taken into account to determine the reset pulse width:  
VDD rise time (vddrst),  
Oscillator startup time (oscrst).  
To determine the capacitor the highest value of these two parameters has to be chosen.  
The reset circuitry is shown in Figure 5.  
Figure 5. Reset Circuitry  
VDD  
Crst  
RST pin  
Internal reset  
Rrst  
Reset input circuitry  
Table 12 and Table 13 give some typical examples for three values of VDD rise times,  
two values of oscillator start-up time and two pull-down resistor values.  
Table 12. Minimum Reset Capacitor for a 50K Pull-down Resistor  
oscrst/vddrst  
5ms  
1ms  
10ms  
1.2µF  
3.9µF  
100ms  
12µF  
820nF  
2.7µF  
20ms  
12µF  
18  
AT89C5115  
4128F–8051–05/06  
 
 
 
 
 
 
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