AT89C5115
Register
Table 11. CKCON Register
CKCON (S:8Fh)
Clock Control Register
7
-
6
5
4
3
2
1
0
WDX2
PCAX2
SIX2
T2X2
T1X2
T0X2
X2
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
-
Do not set this bit.
Watchdog Clock (1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
WDX2
PCAX2
SIX2
Programmable Counter Array Clock (1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
5
4
3
2
1
Enhanced UART clock (MODE 0 and 2) (1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer 2 Clock (1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
T2X2
T1X2
T0X2
Timer 1 Clock (1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer 0 Clock (1)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
CPU Clock
Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all
the peripherals.
0
X2
Set to select 6 clock periods per machine cycle (X2 Mode) and to enable the
individual peripherals ’X2’ bits.
Note:
1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit
has no effect.
Reset Value = x000 0000b
17
4128F–8051–05/06
ATMEL [ ATMEL ]
