AT89C5115
Table 13. Minimum Reset Capacitor for a 15k Pull-down Resistor
oscrst/vddrst
5ms
1ms
2.7µF
10µF
10ms
4.7µF
15µF
100ms
47µF
20ms
47µF
Note:
These values assume VDD starts from 0v to the nominal value. If the time between two
on/off sequences is too fast, the power-supply decoupling capacitors may not be fully
discharged, leading to a bad reset sequence.
During a Normal
Operation (Warm Reset)
Reset pin must be maintained for at least 2 machine cycles (24 oscillator clock periods)
to apply a reset sequence during normal operation. The number of clock periods is
mode independent (X2 or X1).
Watchdog Reset
A 1K resistor must be added in series with the capacitor to allow the use of watchdog
reset pulse output on the RST pin or when an external power-supply supervisor is used.
Figure 6 shows the reset circuitry when a capacitor is used.
Figure 6. Reset Circuitry for a Watchdog Configuration
VDD
Crst
watchdog
1k
RST pin
Internal reset
Rrst
Reset input circuitry
To other on-board circuitry
Figure 7 shows the reset circuitry when an external reset circuit is used.
Figure 7. Reset Circuitry Example Using an External Reset Circuit
VDD
watchdog
External reset
circuit
1k
RST pin
RST
Internal reset
Rrst
Reset input circuitry
To other on-board circuitry
19
4128F–8051–05/06
ATMEL [ ATMEL ]
