Table 110. External 8-bit Bus Cycle – Data Write AC Timings
VDD = 2.7 to 3.3V, TA = -40° to +85°C
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol Parameter
Min
Max
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCLCL
TLHLL
Clock Period
50
50
ALE Pulse Width
2·TCLCL-15
TCLCL-20
TCLCL-20
3·TCLCL-30
6·TCLCL-25
TCLCL-20
4·TCLCL-30
7·TCLCL-20
TCLCL-15
TCLCL-15
TAVLL
Address Valid to ALE Low
Address hold after ALE Low
ALE Low to WR Low
WR Pulse Width
0.5·TCLCL-20
0.5·TCLCL-20
1.5·TCLCL-30
3·TCLCL-25
0.5·TCLCL-20
2·TCLCL-30
3.5·TCLCL-20
0.5·TCLCL-15
TLLAX
TLLWL
TWLWH
TWHLH
TAVWL
TQVWH
TWHQX
WR High to ALE High
Address Valid to WR Low
Data Valid to WR High
Data Hold after WR High
TCLCL+20
0.5·TCLCL+20
23.3.1.3
Waveforms
Figure 23-8. External 8-bit Bus Cycle – Data Read Waveforms
ALE
TLHLL
TLLRL
TRLRH
TRHLH
RD
TRLDV
TRHDZ
TRHDX
TRLAZ
TLLAX
TAVLL
P0
P2
A7:0
D7:0
Data In
TAVRL
TAVDV
A15:8
160
AT89C5132
4173E–USB–09/07
ATMEL [ ATMEL ]
