23.3.3.2
Timings
Table 115. SPI Interface Master AC Timing
VDD = 2.7 to 3.3V, TA = -40° to +85°C
Symbol
Parameter
Min
Max
Unit
Slave Mode
TCHCH
Clock Period
8
TOSC
TOSC
TOSC
ns
TCHCX
Clock High Time
Clock Low Time
SS Low to Clock edge
3.2
3.2
200
100
100
TCLCX
TSLCH, TSLCL
TIVCL, TIVCH
TCLIX, TCHIX
TCLOV, TCHOV
TCLOX, TCHOX
TCLSH, TCHSH
TIVCL, TIVCH
TCLIX, TCHIX
TSLOV
Input Data Valid to Clock Edge
Input Data Hold after Clock Edge
Output Data Valid after Clock Edge
Output Data Hold Time after Clock Edge
SS High after Clock Edge
Input Data Valid to Clock Edge
Input Data Hold after Clock Edge
SS Low to Output Data Valid
Output Data Hold after SS High
SS High to SS Low
ns
ns
100
ns
0
ns
0
ns
100
100
ns
ns
130
130
ns
TSHOX
ns
(1)
TSHSL
TILIH
Input Rise Time
2
µs
µs
ns
ns
TIHIL
Input Fall Time
2
TOLOH
Output Rise Time
100
100
TOHOL
Output Fall Time
Master Mode
TCHCH
Clock Period
4
TOSC
TOSC
TOSC
ns
TCHCX
Clock High Time
1.6
1.6
50
50
TCLCX
Clock Low Time
TIVCL, TIVCH
TCLIX, TCHIX
TCLOV, TCHOV
TCLOX, TCHOX
TILIH
Input Data Valid to Clock Edge
Input Data Hold after Clock Edge
Output Data Valid after Clock Edge
Output Data Hold Time after Clock Edge
Input Data Rise Time
ns
65
ns
0
ns
2
2
µs
TIHIL
Input Data Fall Time
µs
TOLOH
Output Data Rise Time
50
50
ns
TOHOL
Output Data Fall Time
ns
Notes: 1. Value of this parameter depends on software.
2. Test conditions: capacitive load on all pins = 100 pF
164
AT89C5132
4173E–USB–09/07
ATMEL [ ATMEL ]
