AT89C5132
23.3 AC Characteristics
23.3.1
External 8-bit Bus Cycles
23.3.1.1
Definition of Symbols
Table 108. External 8-bit Bus Cycles Timing Symbol Definitions
Signals
Address
Conditions
High
A
D
L
H
L
Data In
ALE
Low
V
X
Z
Valid
Q
R
W
Data Out
RD
No Longer Valid
Floating
WR
23.3.1.2
Timings
Test conditions: capacitive load on all pins = 50 pF.
Table 109. External 8-bit Bus Cycle – Data Read AC Timings
VDD = 2.7 to 3.3V, TA = -40° to +85°C
Variable Clock
Standard Mode
Variable Clock
X2 Mode
Symbol Parameter
Min
Max
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCLCL
TLHLL
TAVLL
TLLAX
TLLRL
TRLRH
TRHLH
TAVDV
TAVRL
TRLDV
TRLAZ
TRHDX
TRHDZ
Clock Period
50
50
ALE Pulse Width
2·TCLCL-15
TCLCL-20
TCLCL-20
3·TCLCL-30
6·TCLCL-25
TCLCL-20
TCLCL-15
Address Valid to ALE Low
Address hold after ALE Low
ALE Low to RD Low
0.5·TCLCL-20
0.5·TCLCL-20
1.5·TCLCL-30
3·TCLCL-25
RD Pulse Width
RD high to ALE High
Address Valid to Valid Data In
Address Valid to RD Low
RD Low to Valid Data
RD Low to Address Float
Data Hold After RD High
Instruction Float After RD High
TCLCL+20
0.5·TCLCL-20
0.5·TCLCL+20
4.5·TCLCL-65
9·TCLCL-65
4·TCLCL-30
2·TCLCL-30
5·TCLCL-30
0
2.5·TCLCL-30
0
0
0
2·TCLCL-25
TCLCL-25
159
4173E–USB–09/07
ATMEL [ ATMEL ]
