AT89C5132
20. Two-wire Interface (TWI) Controller
The AT89C5132 implements a TWI controller supporting the four standard master and slave
modes with multimaster capability. Thus, it allows connection of slave devices like LCD control-
ler, audio DAC, etc., but also external master controlling where the AT89C5132 is used as a
peripheral of a host.
The TWI bus is a bi-directional TWI serial communication standard. It is designed primarily for
simple but efficient integrated circuit control. The system is comprised of 2 lines, SCL (Serial
Clock) and SDA (Serial Data) that carry information between the ICs connected to them. The
serial data transfer is limited to 100 Kbit/s in low speed mode, however, some higher bit rates
can be achieved depending on the oscillator frequency. Various communication configurations
can be designed using this bus. Figure 20-1 shows a typical TWI bus configuration using the
AT89C5132 in master and slave modes. All the devices connected to the bus can be master and
slave.
Figure 20-1. Typical TWI Bus Configuration
AT89C5132
Master/Slave
HOST
Microprocessor
LCD
Display
Audio
DAC
Rp Rp
P1.6/SCL
P1.7/SDA
SCL
SDA
20.1 Description
The CPU interfaces to the TWI logic via the following four 8-bit special function registers: the
Synchronous Serial Control register (SSCON SFR, see Table 26), the Synchronous Serial Data
register (SSDAT SFR, see Table 28), the Synchronous Serial Status register (SSSTA SFR, see
Table 27) and the Synchronous Serial Address register (SSADR SFR, see Table 29).
SSCON is used to enable the controller, to program the bit rate (see Table 26), to enable slave
modes, to acknowledge or not a received data, to send a START or a STOP condition on the
TWI bus, and to acknowledge a serial interrupt. A hardware reset disables the TWI controller.
SSSTA contains a status code which reflects the status of the TWI logic and the TWI bus. The
three least significant bits are always zero. The five most significant bits contains the status
code. There are 26 possible status codes. When SSSTA contains F8h, no relevant state infor-
mation is available and no serial interrupt is requested. A valid status code is available in SSSTA
after SSI is set by hardware and is still present until SSI has been reset by software. Table 20 to
Table 20-6 give the status for both master and slave modes and miscellaneous states.
SSDAT contains a Byte of serial data to be transmitted or a Byte which has just been received. It
is addressable while it is not in process of shifting a Byte. This occurs when TWI logic is in a
defined state and the serial interrupt flag is set. Data in SSDAT remains stable as long as SSI is
set. While data is being shifted out, data on the bus is simultaneously shifted in; SSDAT always
contains the last Byte present on the bus.
SSADR may be loaded with the 7 - bit slave address (7 most significant bits) to which the con-
troller will respond when programmed as a slave transmitter or receiver. The LSB is used to
enable general call address (00h) recognition.
Figure 20-2 shows how a data transfer is accomplished on the TWI bus.
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4173E–USB–09/07
ATMEL [ ATMEL ]
