Bit
Bit Number Mnemonic Description
SPI Rate Bits 0 and 1
Refer to Table 97 for bit rate description.
1 - 0
SPR1:0
Reset Value = 0001 0100b
Note:
1. When the SPI is disabled, SCK outputs high level.
Table 99. SPSTA Register
SPSTA (S:C4h) – SPI Status Register
7
6
5
-
4
3
-
2
-
1
-
0
-
SPIF
WCOL
MODF
Bit
Bit Number Mnemonic Description
SPI Interrupt Flag
Set by hardware when an 8-bit shift is completed.
Cleared by hardware when reading or writing SPDAT after reading SPSTA.
7
SPIF
Write Collision Flag
6
5
WCOL
Set by hardware to indicate that a collision has been detected.
Cleared by hardware to indicate that no collision has been detected.
Reserved
The values read from this bit is indeterminate. Do not set this bit.
-
Mode Fault
4
MODF
-
Set by hardware to indicate that the SS pin is at an appropriate level.
Cleared by hardware to indicate that the SS pin is at an inappropriate level.
Reserved
The values read from these Bits are indeterminate. Do not set these Bits.
3:0
Reset Value = 00000 0000b
Table 100. SPDAT Register
SPDAT (S:C5h) – Synchronous Serial Data Register
7
6
5
4
3
2
1
0
SPD7
SPD6
SPD5
SPD4
SPD3
SPD2
SPD1
SPD0
Bit
Bit Number Mnemonic Description
7 - 0 SPD7:0 Synchronous Serial Data
Reset Value = XXXX XXXXb
130
AT89C5132
4173E–USB–09/07
ATMEL [ ATMEL ]
