AT89C5132
Figure 19-12. Slave SPI Interrupt Policy Flows
SPI Initialization
Interrupt Policy
SPI Interrupt
Service Routine
Select Slave Mode
MSTR = 0
Get Status
Read SPSTA
Select Format
Program CPOL & CPHA
Get Data Received
Read SPDAT
Enable Interrupt
ESPI =1
Prepare New Transfer
Write Data in SPDAT
Enable SPI
SPEN = 1
Prepare Transfer
Write Data in SPDAT
19.4 Registers
Table 98. SPCON Register
SPCON (S:C3h) – SPI Control Register
7
6
5
4
3
2
1
0
SPR2
SPEN
SSDIS
MSTR
CPOL
CPHA
SPR1
SPR0
Bit
Bit Number Mnemonic Description
SPI Rate Bit 2
Refer to Table 97 for bit rate description.
7
6
SPR2
SPEN
SPI Enable Bit
Set to enable the SPI interface.
Clear to disable the SPI interface.
Slave Select Input Disable Bit
Set to disable SS in both master and slave modes. In slave mode this bit has no effect if
CPHA = 0.
Clear to enable SS in both master and slave modes.
5
SSDIS
Master Mode Select
Set to select the master mode.
Clear to select the slave mode.
4
3
2
MSTR
CPOL
CPHA
SPI Clock Polarity Bit(1)
Set to have the clock output set to high level in idle state.
Clear to have the clock output set to low level in idle state.
SPI Clock Phase Bit
Set to have the data sampled when the clock returns to idle state (see CPOL).
Clear to have the data sampled when the clock leaves the idle state (see CPOL).
129
4173E–USB–09/07
ATMEL [ ATMEL ]
