AT89C5132
AT89C5132 captures data from the SI line while the selected slave captures data from the SO
line.
For simplicity, the following figures depict the SPI waveforms in idealized form and do not pro-
vide precise timing information. For timing parameters refer to the Section “AC Characteristics”.
Note:
1. When the peripheral is disabled (SPEN = 0), default SCK line is high level.
Figure 19-5. Data Transmission Format (CPHA = 0)
1
2
3
4
5
6
7
8
SCK Cycle Number
SPEN (Internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
MSB
bit 6
bit 6
bit 5
bit 5
bit 4
bit 4
bit 3
bit 3
bit 2
bit 2
bit 1
bit 1
LSB
LSB
MOSI (from Master)
MISO (from Slave)
MSB
SS (to Slave)
to Capture Point
Figure 19-6. Data Transmission Format (CPHA = 1)
1
2
3
4
5
6
7
8
SCK Cycle Number
SPEN (Internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
MSB
MSB
bit 6
bit 6
bit 5
bit 5
bit 4
bit 4
bit 3
bit 3
bit 2
bit 2
bit 1
bit 1
LSB
MOSI (from Master)
MISO (from Slave)
LSB
SS (to Slave)
Capture Point
19.1.5
SS Management
Figure 19-5 shows an SPI transmission with CPHA = 0, where the first SCK edge is the MSB
capture point. Therefore the slave starts to output its MSB as soon as it is selected: SS asserted
to low level. SS must then be deasserted between each byte transmission (see Figure 19-7).
SPDAT must be loaded with data before SS is asserted again.
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4173E–USB–09/07
ATMEL [ ATMEL ]
