Figure 71. Audio Processor Block Diagram
Audio Buffer
CPU/DFC
Audio DAC
Interface
Audio Codec
Digital Audio
Processor
CPU
Audio Buffer
The audio buffer receives the audio data flow coming from DFC or the C51. It is based
on 1 Kbyte of dual-port RAM.
Buffer Description
The audio buffer can be accessed in read or write mode by both C51 and DFC. Access
selection is done by the ABACC bit in APCON1. Considering the DFC, two channels
can be established at the same time one in which the audio processor is the source and
one in which the audio processor is the destination. To achieve such scheme, the audio
buffer can be configured using ABSPLIT in APCON1 as one (see Figure 72a) or two
(see Figure 72b) buffers, each containing two data packets of 512 or 256 bytes size.
Figure 72. Audio Buffer Configuration
CPU (APDAT)
512-byte
512-byte
DFC
rd pointer
wr pointer
a. Single Buffer (ABSPLIT= 0)
CPU (APDAT)
DFC
256-byte
wr pointer
256-byte
256-byte
CPU (APDAT)
DFC
256-byte
rd pointer
b. Double Buffer (ABSPLIT= 1)
Internal read or write pointers can be reset at any time by setting respectively ABRPR
and ABWPR bits in APCON1. These bits are automatically reset by hardware.
Buffer Management
The C51 reads from or writes to the buffer through the APDAT register. Management is
controlled by a couple of flags informing the user that data can be written to the buffer or
read from the buffer depending on the current operation.
In case of write (audio stream decoding or codec firmware update) APREQI flag in
APINT is set every time a data packet (256 or 512 bytes) can be written to the buffer i.e.
buffer empty or half full. APREQI is cleared when the buffer becomes full.
In case of read (audio stream encoding) APRDYI flag in APINT is set every time a data
packet (256 or 512 bytes) can be retrieved from the buffer i.e. buffer full or half full.
APRDYI is cleared when the buffer becomes empty.
These flags can generate an interrupt when APREQE bit and APRDYE bit in APIEN are
respectively set (see Section “Interrupts”).
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