“Manual” Mode
The TXOUT bit is set by hardware when the current bank becomes free. This triggers an
interrupt if the TXOUTE bit is set. The FIFOCON bit is set at the same time. The CPU
writes into the FIFO and clears the FIFOCON bit to allow the USB controller to send the
data. If the OUT Pipe is composed of multiple banks, this also switches to the next data
bank. The TXOUT and FIFOCON bits are automatically updated by hardware regarding
the status of the next bank.
Example with 1 OUT data bank
DATA
(bank 0)
OUT
ACK
HW
OUT
TXOUT
SW
SW
FIFOCON
SW
SW
write data from CPU
BANK 0
write data from CPU
BANK 0
Example with 2 OUT data banks
DATA
(bank 0)
DATA
(bank 1)
OUT
ACK
HW
OUT
ACK
TXOUT
SW
SW
SW
FIFOCON
SW
SW
write data from CPU
BANK 0
write data from CPU
BANK 1
write data from CPU
BANK0
Example with 2 OUT data banks
DATA
ACK
DATA
ACK
OUT
OUT
(bank 0)
(bank 1)
HW
TXOUT
SW
SW
SW
FIFOCON
SW
SW
write data from CPU
BANK 0
write data from CPU
BANK 1
write data from CPU
BANK0
132
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
