“Autoswitch” Mode
In this mode, the clear of the FIFOCON bit is performed automatically by hardware each
time the Pipe bank is empty. The firmware has to check if the next bank is empty or not
before reading the next data. On RXIN interrupt, the firmware reads a complete bank. A
new interrupt will be generated each time the current bank contains data to read.
The acknowledge of the RXIN interrupt is always performed by software.
CRC Error (isochronous only) A CRC error can occur during IN stage if the USB controller detects a bad received
packet. In this situation, the STALLEDI/CRCERRI interrupt is triggered. This does not
prevent the RXINI interrupt from being triggered.
Interrupt
Figure 67 shows all the host interrupts sources while Figure 68 details the pipe interrupt
sources.
Figure 67. USB Host Controller Interrupt System
HWUPI
UHINT.6
HWUPE
UHIEN.6
HSOFI
UHINT.5
HSOFE
UHIEN.5
RXRSMI
UHINT.4
RXRSME
UDIEN.4
RSMEDI
UHINT.3
USB Host
Interrupt
RSMEDE
UHIEN.3
RSTI
UHINT.2
RSTE
UHIEN.2
DDISCI
UHINT.1
DDISCE
UHIEN.1
DCONNI
UHINT.0
DCONNE
UHIEN.0
134
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
