AT85C51SND3Bx
Registers
Table 72. IEN0 Register
IEN0 (0.A8h) – Interrupt Enable Register 0
7
6
5
4
3
2
1
0
EA
EAUP
EDFC
ES
ET1
EX1
ET0
EX0
Bit
Bit
Number
Mnemonic Description
Enable All Interrupt Bit
Set to enable all interrupts.
Clear to disable all interrupts.
7
EA
If EA = 1, each interrupt source is individually enabled or disabled by setting or
clearing its interrupt enable bit.
AUP Interrupt Enable Bit
6
5
4
3
2
1
0
EAUP
EDFC
ES
Set to enable audio processor interrupt.
Clear to disable audio processor interrupt.
DFC Enable Bit
Set to enable data flow interrupt.
Clear to disable data flow interrupt.
SIO Interrupt Enable Bit
Set to enable serial port interrupt.
Clear to disable serial port interrupt.
T1 Overflow Interrupt Enable Bit
ET1
Set to enable timer 1 overflow interrupt.
Clear to disable timer 1 overflow interrupt.
EX1 Interrupt Enable bit
EX1
ET0
Set to enable external interrupt 1.
Clear to disable external interrupt 1.
T0 Overflow Interrupt Enable Bit
Set to enable timer 0 overflow interrupt.
Clear to disable timer 0 overflow interrupt.
EX0 Interrupt Enable Bit
EX0
Set to enable external interrupt 0.
Clear to disable external interrupt 0.
Reset Value = 0000 0000b
59
7632A–MP3–03/06
ATMEL [ ATMEL ]
