AT85C51SND3Bx
Interrupt System
The AT85C51SND3Bx, like other control-oriented computer architectures, employ a
program interrupt method. This operation branches to a subroutine and performs some
service in response to the interrupt. When the subroutine completes, execution resumes
at the point where the interrupt occurred. Interrupts may occur as a result of internal
AT85C51SND3Bx activity (e.g., timer overflow) or at the initiation of electrical signals
external to the microcontroller (e.g., keyboard). In all cases, interrupt operation is pro-
grammed by the system designer, who determines priority of interrupt service relative to
normal code execution and other interrupt service routines. All of the interrupt sources
are enabled or disabled by the system designer and may be manipulated dynamically.
A typical interrupt event chain occurs as follows:
•
•
•
An internal or external device initiates an interrupt-request signal. The
AT85C51SND3Bx, latch this event into a flag buffer.
The priority of the flag is compared to the priority of other interrupts by the interrupt
handler. A high priority causes the handler to set an interrupt flag.
This signals the instruction execution unit to execute a context switch. This context
switch breaks the current flow of instruction sequences. The execution unit
completes the current instruction prior to a save of the program counter (PC) and
reloads the PC with the start address of a software service routine.
•
The software service routine executes assigned tasks and as a final activity
performs a RETI (return from interrupt) instruction. This instruction signals
completion of the interrupt, resets the interrupt-in-progress priority and reloads the
program counter. Program operation then continues from the original point of
interruption.
Six interrupt registers are used to control the interrupt system:
–
Two 8-bit registers are used to enable separately the interrupt sources: IEN0
and IEN1 registers (see Table 72 and Table 73).
–
Four 8-bit registers are used to establish the priority level of the different
sources: IPH0, IPL0, IPH1 and IPL1 registers (see Table 74 to Table 77).
Interrupt System
Priorities
Each interrupt sources of the AT85C51SND3Bx can be individually programmed to one
of four priority levels. This is accomplished by one bit in the Interrupt Priority High regis-
ters (IPH0 and IPH1) and one bit in the Interrupt Priority Low registers (IPL0 and IPL1).
This provides each interrupt source four possible priority levels according to Table 70.
Table 70. Priority Levels
IPHxx
IPLxx
Priority Level
0
0
1
1
0
1
0
1
0
1
2
3
Lowest
Highest
A low-priority interrupt is always interrupted by a higher priority interrupt but not by
another interrupt of lower or equal priority. Higher priority interrupts are serviced before
lower priority interrupts. The response to simultaneous occurrence of equal priority inter-
rupts is determined by an internal hardware polling sequence detailed in Table 71.
Thus, within each priority level there is a second priority structure determined by the
polling sequence. The interrupt control system is shown in Interrupt Control System.
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7632A–MP3–03/06
ATMEL [ ATMEL ]
