Table 75. IPH1 Register
IPH1 (0.B3h) – Interrupt Priority High Register 1
7
6
5
4
3
2
1
0
-
-
IPHMMC
IPHNFC
IPHSPI
IPHSPI
IPHKB
IPHUSB
Bit
Bit
Number
Mnemonic Description
Reserved
7-6
5
-
The value read from these bits is always 0. Do not set these bits.
MMC/SD Interrupt Priority Level Msb
IPHMMC
IPHNFC
IPHSPI
IPHPSI
IPHKB
Refer to Table 70 for priority level description.
NFC Interrupt Priority Level Msb
4
Refer to Table 70 for priority level description.
SPI Interrupt Priority Level Msb
3
Refer to Table 70 for priority level description.
PSI Interrupt Priority Level Msb
2
Refer to Table 70 for priority level description.
KBD Interrupt Priority Level Msb
1
Refer to Table 70 for priority level description.
USB Interrupt Priority Level Msb
0
IPHUSB
Refer to Table 70 for priority level description.
Reset Value = 0000 0000b
62
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
