AT85C51SND3Bx
Table 74. IPH0 Register
IPH0 (0.B7h) – Interrupt Priority High Register 0
7
6
5
4
3
2
1
0
-
IPHAUP
IPHDFC
IPHS
IPHT1
IPHX1
IPHT0
IPHX0
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
5
4
3
2
1
0
-
The value read from this bit is indeterminate. Do not set this bit.
AUP Interrupt Priority Level Msb
IPHAUP
IPHDFC
IPHS
Refer to Table 70 for priority level description.
DFC Interrupt Priority Level Msb
Refer to Table 70 for priority level description.
SIO Interrupt Priority Level Msb
Refer to Table 70 for priority level description.
T1 Interrupt Priority Level Msb
IPHT1
IPHX1
IPHT0
IPHX0
Refer to Table 70 for priority level description.
EX1 Interrupt Priority Level Msb
Refer to Table 70 for priority level description.
T0 Interrupt Priority Level Msb
Refer to Table 70 for priority level description.
EX0 Interrupt Priority Level Msb
Refer to Table 70 for priority level description.
Reset Value = X000 0000b
61
7632A–MP3–03/06
ATMEL [ ATMEL ]
