Bit
Bit
Number
Mnemonic Description
Stall Interrupt Flag
Set by hardware to signal that a STALL handshake has been sent, or that a CRC
error has been detected in a OUT isochronous endpoint.
Shall be cleared by software. Setting by software has no effect.
1
0
STALLI
TXINI
Transmitter Ready Interrupt Flag
Set by hardware to signal that the current bank is free and can be filled. An
interrupt (EPINTx) is triggered (if enabled).
Shall be cleared by software to handshake the interrupt. Setting by software has
no effect.
This bit is inactive (cleared) if the endpoint is an OUT endpoint.
Reset Value = 0000 0000b
Table 127. UEIENX Register
UEIENX (1.D2h) – USB Endpoint Interrupt Enable Register
7
6
5
4
3
2
1
0
FLERRE
NAKINE
-
NAKOUTE
RXSTPE
RXOUTE
STALLE
TXINE
Bit
Bit
Number
Mnemonic Description
Flow Error Interrupt Enable Flag
Set to enable an endpoint interrupt (EPINTx) when OVERFI or UNDERFI are
7
FLERRE
sent.
Clear to disable an endpoint interrupt (EPINTx) when OVERFI or UNDERFI are
sent.
NAK IN Interrupt Enable Bit
6
5
4
NAKINE
-
Set to enable an endpoint interrupt (EPINTx) when NAKINI is set.
Clear to disable an endpoint interrupt (EPINTx) when NAKINI is set.
Reserved
The value read from these bits is always 0. Do not set these bits.
NAK OUT Interrupt Enable Bit
NAKOUTE
Set to enable an endpoint interrupt (EPINTx) when NAKOUTI is set.
Clear to disable an endpoint interrupt (EPINTx) when NAKOUTI is set.
Received SETUP Interrupt Enable Flag
3
2
1
0
RXSTPE
RXOUTE
STALLE
TXINE
Set to enable an endpoint interrupt (EPINTx) when RXSTPI is sent.
Clear to disable an endpoint interrupt (EPINTx) when RXSTPI is sent.
Received OUT Data Interrupt Enable Flag
Set to enable an endpoint interrupt (EPINTx) when RXOUTI is sent.
Clear to disable an endpoint interrupt (EPINTx) when RXOUTI is sent.
Stall Interrupt Enable Flag
Set to enable an endpoint interrupt (EPINTx) when STALLI is sent.
Clear to disable an endpoint interrupt (EPINTx) when STALLI is sent.
Transmitter Ready Interrupt Enable Flag
Set to enable an endpoint interrupt (EPINTx) when TXINI is sent.
Clear to disable an endpoint interrupt (EPINTx) when TXINI is sent.
Reset Value = 0000 0000b
124
AT85C51SND3Bx
7632A–MP3–03/06
ATMEL [ ATMEL ]
